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User talk:Stevewilliams
Hello Leave notes here for Stephen Williams. tgt-fpga and synthesis Hi Stephen, Thank you for your great work on Icarus. I've been trying to use the fpga target for synthesis. It does not seem to be included in the normal windows or linux build. When I try to manually compile the fpga target there are compilation errors in xilinx.c etc. A quick search on the web showed that others have had the same problem. Is there a known solution to this issue? Are there future plans to support synthesis? Mac ports troubles - The MacPorts Portfile or Icarus was updated to Version 0.8.2. I tried getting 0.8.3 to work but didn't have success. I'll try again and lt you know what happens. - The present version of Icarus under Fink is 0.8.1. I quit using Fink since the packages weren't updated as often as MacPorts and I'm perfectly happy using the command line--even on a Mac. Update: I tried again to compile 0.8.3 on Mac OS X 10.3.9 without success. I've submitted a bug. Update: The bug appears to be fixed. Is there a list, an archive, or some common place I can go to where all the patches for Icarus 0.8.3 are stored? - The place to go for the latest patched version is the CVS repository. In the case of the 0.8 stable release, get the branch-v0.8 branch from CVS. Or wait for the next subrelease. I make those periodically to connect all the bug fixes made to the stable branch. See the Installation Guide for details. Stevewilliams 17:57, 2 November 2006 (UTC) The current snapshots are developed on Mac OS X 10.3, dispite my claims that Icarus Verilog is written on Linux:-) However, I actually work on Icarus Verilog bugs in both places and the 0.8 branch almost exclusively on Linux. So it is possible that the stable release developed build troubles. Any troubles that you find are candidates for bug reports. --Stevewilliams 16:30, 1 November 2006 (UTC) tgt-verilog I'm not sure where to post this question so I'm putting it here. I need to be able to create a version of a Verilog design that is elaborated i.e. all pre-processing done, flattened and all parameters replaced with constants, etc. I'd like to be able to use iverilog for this. It appears the code in the subdirectory tgt-verilog does this or almost does this. However, it is not a part of the regular install so I have no idea about the current state of it. Is this something a mere mortal could get going or does it require an expertise beyond C programming skills? Please advise. ---- -- The "verilog" target needs some love to get it back into action. In the v0.8 branch it has simply collected bit rot. In the devel trunk it needs to be updated to support the new ivl_target API. The skills needed to work on this target are: * Good C skills. (C++ not necessary in the loadable targets.) * Good Verilog skills. * An understanding of the ivl_target API. As for support questions, the Icarus Verilog home page should have the links you need. ---- I don't write C programs everyday but I've been using C for over 20 years. I write Verilog almost everyday and have been doing so for nearly 15 years. Is there documentation for the API in addition to: * ivl_target.h * http://iverilog.wikia.com/wiki/Using_Loadable_Target_API ??? What is the best example of using the API? * tgt-vvp ??? Please advise. ---- The ivl_target.h header file is the last word in the API definition. Examples that use that API are the tgt-null, which is the most minimal target possible, and tgt-stub which dumps everything. Actually, fleshing out the ivl_target API in this wiki is a task that needs doing:-) NOTE The API changes significantly from the 0.8 and the devel trees. New code generators should be written against the API used in the devel tree. Stevewilliams 19:12, 29 November 2006 (UTC) ---- My plan is to make a "verilog" target using the devel tree. I wasn't planning on resuscitating the one for 0.8. I hope you won't mind the occasional question. Anything you clarify will find its way into the Wiki. iverilog return value? Hi, I'm using a python script to run Icarus and GTKWave, and I would like to know if there is any returned value for errors by Icarus before GTKWave jumps in. So I've been wondering if the "iverilog" command returns any value so I can check it to see if there is any errors. I would really appreciate it if you have any other suggestions on this issue as well. ---- Yes the iverilog command (compiler) works like most other UNIX programs and returns a non-zero value for failure. The run time (vvp) normally returns zero. We do have an Icarus specific system task $finish_and_return() that can be used to exit and set the run time return value from the Verilog code. This can be used to indicate Verilog failures to scripts. Look at the Perl script we have for the test suite. It does a fairly good job of categorizing the various failures and should be easily translated to Python. Cary 21:43, 28 December 2008 (UTC) Thanks for your reply. Can you please tell me where can I find documentation for the system task that you mentioned and any other icarus useful tasks. In addition where can I find the test suite with the Perl script. ---- The text provided the documentation "$finish_and_return()". This quits the simulator and return the provided value. We need better documentation of the various enhancements. Some information is on this wiki for the rest the source code is the best bet. How to get the test suite can be found on the Icarus web page (http://www.icarus.com/eda/verilog/). Cary 19:14, 8 January 2009 (UTC) Unable to compile hello.v I installed Icarus onto my laptop which has the Vista (64-bit) OS and added the path to the iverilog executable. If i run a command line prompt, move to the directory that holds the hello.v verilog code, and type iverilog i get a list of iverilog options. However when i type iverilog -o hello hello.v i get 'C:Program' is not recognized as an internal or external command operable program or batch file. Is there an embedded path in the iverilog source that expects the source location to be in C:\Program. I installed the Icarus application using a download of version verilog-0.9.1, this was a precompiled version from http://bleyer.org/icarus/ Any help to resolve this would be greatly appreciated. regards, Dean Icarus does not currently support a space in any paths. We are working on this and hope to have this fixed for the next release. The fix is to install Icarus into a path with out a space c:/Icarus instead of c:/Program Files. Cary 03:53, October 31, 2009 (UTC) V0.9.2 should now support a space in the install path under windows. Error: Module was already declared here Hi steve, I am trying to write a code for a 2to4decoder. Now when i write the whole code in one file, i.e the test bench and the main program in one file, i get no compilation errors. However, when written in different files, i get an error that says cannot reference a module. To fix this, I included the main code in the testbench code with the include statement. Now when the test bench is compiled alone, i get no errors. However, when compiled together, i get an error. My compile line and error is shown below: iverilog 2to4decoder.v 2to4decoder_tb.v -o 2to4dec 2to4decoder.v:11: Module dec2to4 was already declared here: 2to4decoder.v:1 '' Can you tell me how to rectify this? -Viks Since you are already including the file from the test bench there is no need to place it on the command line. The 2to4decoder.v file is being included twice and Icarus is correctly telling you you are doing something wrong. Including both file on the command line is the correct way to compile multiple files if you are not using an include. You do not compile the files individually. Cary 15:29, September 29, 2009 (UTC) No top level modules, and no -s option. Hi, Can someone explain this error to me? - Viks The short answer is that Icarus can not find a top level module. A top level module is a module that is not called by any other module. In very weird and rare situation something like this could exist, but it is almost always a problem in the users code. For the rare cases where this does exist the compiler takes a -s flag that explicitly states what module should be used as the top level module. Cary 15:34, September 29, 2009 (UTC) ---- Alright, thanks a lot Cary for your help. - Viks error: Gate count of 1 does not match net width of 8 at pin 1. Hi, Can someone explain me this error? The comparator points to this line xor gate1 7:0 (c,b,a); - Viks This works for me using the latest development, V0.8 and V0.9 releases. We need more context to figure these kind of things out (what version of Icarus are you using, a complete file that demonstrates the problem, the OS you are using, etc.). This is likely a bug on your part, but Icarus is not being very helpful in telling you the exact problem. Another helpful debug flag is -delaborate, this will print a lot of information as the circuit is being elaborated. You can look at this and see where things are not going as expected. reg 7:0 a, b; wire 7:0 z; xor gate1 7:0 (z, a, b); Cary 18:42, September 30, 2009 (UTC) ---- Thanks again Cary, I am not getting the error now but the program does not function the way it has to. My lines were similar to yours but I guess I will check again. Thanks for the tip. Unable to bind wire/reg/memory `test' in: Error Hi, This is the error I get when I add this in test bench initial begin $dumpfile("test.vcd"); $dumpvars(0,test); end '' Is there something I have missed? Is there a good link that explains how to use a GTKwave or a synthesizer with iverilog? Thanks in advance, Vikram I'm guessing you are trying to dump the contents of module test, but you have mistyped something or module test does not exist. Again with out a FULL example that demonstrates the problem there's not much we can do but guess. As a gentle reminder this is not a general Verilog training site and some of these questions are borderline. Once you have dumped a VCD, etc. file read the fine GTKWave manual. It will explain everything you need to know regarding how to use it. A synthesis flow is very tool specific so you are on your own figuring that out. Cary 15:25, October 2, 2009 (UTC) verilog-AMS support hi, I was trying to do some minimal verilog-ams compiles to see how/if icarus verilog supported it. i seem to run into issues parsing the disciplines.vams file. is this expected behavior? if that should work i'll go back and try to figure out the problem. i just wanted to know the level of support with verilog-ams, as i wasn't able to clearly discern the current limitations from the wiki. '''here is what i am trying to compile' // A sinusoidal Source `include "constants.vams" // for definition of `M_PI = 3.1415.... `include "disciplines.vams" module vsin (p,n); parameter real amplitude = 1.0; parameter real freq = 50.0; parameter real phase = 0.0; inout p; inout n; electrical p; electrical n; analog begin @(initial_step) V(p,n) <+ 0.0 ; V(p,n) <+ amplitude * sin(2.0 * `M_PI * freq * $abstime + phase); end endmodule my command line /usr/bin/iverilog -gverilog-ams -osinsrc.out -svsin sinsrc.vams and the output /usr/lib64/ivl/include/disciplines.vams:9: syntax error I give up. thanks! -- 13:37, October 30, 2009 (UTC) ---- Support for VAMS is not complete at this time. We expect almost nothing but a few simple things (constants, some system functions, parameters with ranges, etc.) to work correctly. You can create a sin source in normal Verilog using a real signal (wire real) and an appropriately equation for the $sin() math function and something to trigger the function to evaluate. Just calling one of the time functions does not cause a continuous assign to trigger. I can post an example if needed, but this should be enough if all you are trying to do is create a sin source in Icarus. I also reformatted your example to get it to display better. Cary 04:07, October 31, 2009 (UTC) Compile multiple files with Icarus Can I ask, how I compile multiple files with icarus verilog? I have a file "test.v" , which have 2 includes : e.g. `include "in1.v" `include "in2.v" If I do "iverilog test.v", it throws the following message : "test.v:51: Include file in1.v not found No top level modules, and no -s option." I also tried "iverilog test.v ~/...absolute_path/in1.v ~/...absolute_path/in2.v" , but it stills shows the same message, does anyone know what to do? ---- Yes, and the answer is on this wiki in the user guide section/iverilog preprocessor flags, but the quick answer is, use the -I flag to add the directory with the include files to the include file search path. You can also specify the full path when you include the file. Icarus does not allow compiling files individually you need to give it all the files either on the command line, in an include path or a library path. Cary 07:28, January 17, 2010 (UTC) Conflicts Can I ask, how I can see where and what are the conflicts (shift-reduce), that are thrown when I "make install" the icarus verilog? (As I use/transform some of the build-in rules) ---- This should appear during plain make. Read the bison manual, read the bison/flex book, look in the .output file and try to enjoy what can be a painful process. Cary 22:54, February 2, 2010 (UTC) Conflicts Again Alla that you told me, I already know... First I can't find where is the ".output" that usually being made, and second the output file says clearly in what particularly file-line it is thrown (what rules have what conflict) ? An example that I have a conflict, is : expr_primary : '(' expr_mintypmax ')' I try to insert block-code {}, inside the right part, and specific : expr_primary : '(' --> { printf("T E S T\n"); } <-- expr_mintypmax ')' and it throws conflicts in making/build. As far as I know, it shouldnt, as this rule "expr_primary -> ...", does not have another right part that it is also begins with '('. I also saw that I had already 1 conflict (before the transformation of this rule). Could this 1 already-exist conflict, make a "conflict-less" transformation (if the transformation I want to do, is truly not making conflicts), to throw conflicts? If it does so, that's why I try to find, how to fix the previous conlfict (although it hasn't influenced the correctness of the results of the work I do), and where the conflicts are clearly listed? Otherwise, could you suggest, or know why this transformation, throws additional conflicts? Thank you in advance... ---- If you are using parse.y then the output file will be parse.output in the compilation directory. You may have to tweak one of the bison flags to get better debugging output, but I believe it is already set up correctly. You need to look at the output file and figure out why bison is making the choice it is and then figure out how to change things to make it work as you want. Right now neither Steve or I have much free time to help, and I'm not certain how any of this is helping Icarus. Since this is a bison problem not an Icarus problem you may want to see if you can find a bison/yacc support site. Cary 18:50, February 3, 2010 (UTC) Segmantation/Debugging I also want to ask, if there is a specific way to find in what actual line, a segmentation it is thrown? Because I only edit the "parse.y" file, and when I have a segmentation, the segmentation line error always points to a different file line (which I never edit it), rather than the file (parse.y) that I edit, and it is logically where it is thrown... ---- The program is likely failing because you are passing bad data to the rest of the compile and something in the compiler is then failing. So yes, just changing the parser can cause other things in the compiler to crash. You can use valgrind or gdb to figure out exactly where this is crashing. With that information and some thought you should be able to understand why you parser change is crashing the compiler. Cary 18:43, February 3, 2010 (UTC) Impossilble Conflict Sorry to bother you again, and thanks for your previous answers. I fix the previous conflicts, but now it throws a conflict, that -as far as I know- is not logic. It throws shift/reduce conflicts between 2 completely different rules : 1) expr_primary : '(' expr_mintypmax ')' 2) specparam : PATHPULSE_IDENTIFIER '=' '(' . expression ',' expression ')' The reason is, because I insert a block of code { }, at the 1st rule, after the '(' : expr_primary : '(' { printf("T E S T \n"); } expr_mintypmax ')' But as I see, there is only 1 right part of the rule "expr_primary -> ..." , that starts with '('. So it shouldn't throw any conflict at all. But it throws the conflict between 2 completely different rules (I don't think it is reasonable, thinking the compilers theory, that I know). I also couldn't understand what is "PATHPULSE_IDENTIFIER", so to know if it influences the result, and it is responsible for the conflict, although it is not logic. The conflict (from "parse.output") exactly is the following : ************ expr_primary: '(' . @28 expr_mintypmax ')' specparam: PATHPULSE_IDENTIFIER '=' '(' . expression ',' expression ')' ************ ---- Obviously this is not an impossible conflict and you are missing some interrelationship between the two rules. Well I suppose it could be a bison bug, but no matter, this is not an Icarus issue. PATHPULSE$ is a special specparam. Cary 22:26, February 6, 2010 (UTC) Ad free Hi! Would you like this wiki to be ad-free? I'm looking for wikis to be part of a new program which would remove all ads from the wiki for $19.95/month. If you are interested, please be visit here to sign up. if you have any questions! - sannse (help forum | blog) 05:46, June 2, 2010 (UTC) Hi. =) Hi there. I'm canvassing (read: mass-spamming) all the programming wikis that I haven't contacted before to see whether you would like to exchange links with the Programmer's Wiki. Several ways of doing so are detailed here, and my favorite is the footer that lists all the computer wikis (by which you already get links from those displaying it). Also, the Programmer's Wiki provides a self-titled page to any wiki about programming; we consider all such wikis as extensions of "ours." So please let me know what you think. --Jesdisciple (talk) 22:26, June 22, 2010 (UTC) Does anyone knows how to install icarus Verliog on Windows. I downloaded the Verilog 0.0.3 tar file and unzipped it. It has many files and folders but i don't see any setup files. I am new to verilog. Your help is appreciated. Thanks Look in the installation guide in this very Wiki. There is a section for installing on Windows. Stevewilliams 17:20, November 9, 2010 (UTC) Verilog backend using LLVM Steve, I have just started looking at Icarus and saw your comments from few years ago about LLVM. Have you done any additional work in that area? i.e. are you aware of any Verilog backend for LLVM? Assumingly the verilog parser creates some kind of AST and that can be converted to JIT and then use LLVM (with generic and custon optimization passes) to generate an executable model. Thanks, Vlad Vlad, I'm obviously not Steve, but I know neither he or I have had any time to look at LLVM. This is a bit more complicated than just generating an AST that gets dumped to LLVM. Verilog has 4-state logic and other run time requirements that also need to be addressed using either common routines or enhancements to LLVM. We've been busy with other things so have not had time to look at this. Slightly LLVM related is that the latest Icarus compiles cleanly using clang/clang++ (tested on Ubuntu 11.10). --Cary 20:02, December 16, 2011 (UTC) bash: ./configure: No such file or directory Hello everyone, i am new in this community. I have tried to install the package from source but i stacked in the very first steps. The command ./configure is not working and the sh ./configure will not work either. The message is that no such file or directory exists. Thank you in advance I try to add the command $fsdbdumpfile into the testbench for fsdb file exporting. However, the Icarus will show error message: function $fsdbDumpfile() not defined by any module. I know that there are solutions that Modelsim and VCS can also dump fsdb files. Can the solutions for Modelsim and VCS also work for Icarus simulator? If not, how can we dump fsdb file through Icarus verilog simulator? Thanks for your help ! 04:56, September 8, 2015 (UTC)bhaskar